0.0 Welcome and About Course

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module items
0.01 Start here
0.1 Meet Paul Chow (LEC0103)
0.2 Meet Belinda Wang (LEC0101)
0.3 Meet Bruno Korst (LEC0102)
0.4 Quercus Module Organization 0.4 Quercus Module Organization has been completed
0. 5 Syllabus, Midterm Date, Topic/Lab Schedule, Piazza Setup 0. 5 Syllabus, Midterm Date, Topic/Lab Schedule, Piazza Setup has been completed
0.0 Piazza Discussion ThreadThis is an external link.

Labs

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Guides, Tutorials, other info Guides, Tutorials, other info has been completed
Lab 1 Lab 1 has been completed
Lab 2 Lab 2 has been completed
Lab 3
Lab 4 Lab 4 has been completed
Lab 5 Lab 5 has been completed
Lab 6 Lab 6 has been completed
Lab 7 Lab 7 has been completed
Lab 8

1.0 Introduction

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1.1 Motivation and Where this course fits 1.1 Motivation and Where this course fits has been completed
1.0 Piazza Discussion ThreadThis is an external link.

2.0 Number Systems

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2.1 Binary, decimal and hexadecimal numbers 2.1 Binary, decimal and hexadecimal numbers has been completed
2.0 Solutions
2.0 Piazza discussion threadThis is an external link.

3.0 Logic Circuits and Gates

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module items
3.0 Introduction
3.1 Light Bulb Logic Truth Table 3.1 Light Bulb Logic Truth Table has been completed
3.2 Logic Gates 3.2 Logic Gates has been completed
3.3 Timing Diagrams 3.3 Timing Diagrams has been completed
3_solutions.pdf
3.0 Piazza Discussion ThreadThis is an external link.

4.0 Boolean Algebra

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module items
4.0 Introduction
4.1 Boolean Algebra (Part 1) 4.1 Boolean Algebra (Part 1) has been completed
4.2 Boolean algebra (Part 2) 4.2 Boolean algebra (Part 2) has been completed
4.3 Boolean Algebra Design Example 4.3 Boolean Algebra Design Example has been completed
4.4 Venn Diagrams 4.4 Venn Diagrams has been completed
4.0 Solutions
4.0 Piazza Discussion ThreadThis is an external link.

5.0 Circuit Synthesis

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5.0 Introduction
5.1 Sum of Products 5.1 Sum of Products has been completed
5.2 SoP Example (NAND-NAND) 5.2 SoP Example (NAND-NAND) has been completed
5.3 Product of Sums 5.3 Product of Sums has been completed
5.4 PoS Example (NOR-NOR) 5.4 PoS Example (NOR-NOR) has been completed
5.5 Cost 5.5 Cost has been completed
5.6 Multiplexer Design 5.6 Multiplexer Design has been completed
5.7 Multi-bit Multiplexer 5.7 Multi-bit Multiplexer has been completed
5.8 7-Segment Display 5.8 7-Segment Display has been completed
5.0 Solutions
5.0 Piazza Discussion ThreadThis is an external link.

6.0 Verilog Introduction

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module items
6.0 Introduction
6.1 About Verilog 6.1 About Verilog has been completed
6.2 First Verilog 6.2 First Verilog has been completed
6.3 Verilog Bit Vectors 6.3 Verilog Bit Vectors has been completed
6.4 Verilog Hierarchy 6.4 Verilog Hierarchy has been completed
6.5 7-Segment Display 6.5 7-Segment Display has been completed
6.6 Hex Display 6.6 Hex Display has been completed
6.0 Solutions
6.0 Piazza Discussion ThreadThis is an external link.

7.0 Intro to FPGAs

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module items
7.0 Introduction
7.1 FPGA Introduction 7.1 FPGA Introduction has been completed
7.2 FPGA Computer Aided Design 7.2 FPGA Computer Aided Design has been completed
7.0 Solutions
7.0 Piazza Discussion ThreadThis is an external link.

8.0 Adders

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8.1 Adders 8.1 Adders has been completed
8.0 Solutions
For Fun: Is "Digital" logic really digital?
8.0 Piazza Discussion ThreadThis is an external link.

9.0 Verilog

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9.0 Introduction
9.1 Verilog Always Block 9.1 Verilog Always Block has been completed
9.2 Verilog Case Statement 9.2 Verilog Case Statement has been completed
9.0 Solutions
9.0 Piazza Discussion ThreadThis is an external link.

10.0 Logic Optimization

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10.0 Introduction
10.1 Goal of Optimization 10.1 Goal of Optimization has been completed
10.2 Literal Implicant Cover 10.2 Literal Implicant Cover has been completed
10.3 Minimization 4-5 Variables 10.3 Minimization 4-5 Variables has been completed
10.4 K-maps PoS 10.4 K-maps PoS has been completed
10.5 Incompletely Specified K-map 10.5 Incompletely Specified K-map has been completed
10.0 Solutions
10.0 Piazza Discussion ThreadThis is an external link.

11.0 Sequential Circuits

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11.0 Introduction
11.1 Intro to Sequential Circuits 11.1 Intro to Sequential Circuits has been completed
11.2 RS Latch 11.2 RS Latch has been completed
11.3 Gated RS Latch 11.3 Gated RS Latch has been completed
11.4 Gated D Latch 11.4 Gated D Latch has been completed
11.5 Flip Flops 11.5 Flip Flops has been completed
11.6 Set Reset 11.6 Set Reset has been completed
11.7 FFs In FPGAs 11.7 FFs In FPGAs has been completed
11.0 Solutions
11.0 Piazza Discussion ThreadThis is an external link.

12.0 Verilog Sequential Circuits

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12.0 Introduction
12.1 The Latch 12.1 The Latch has been completed
12.2 The Flip Flop 12.2 The Flip Flop has been completed
12.3 Resets 12.3 Resets has been completed
12.0 Solutions
12.0 Piazza Discussion ThreadThis is an external link.

13.0 Registers

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13.0 Introduction
13.1 Registers Basic 13.1 Registers Basic has been completed
13.2 Shift Register 13.2 Shift Register has been completed
13.3 Shift Register with Parallel Load 13.3 Shift Register with Parallel Load has been completed
13.0 Solutions
13.0 Piazza Discussion ThreadThis is an external link.

14.0 Verilog Statements

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14.0 Introduction 14.0 Introduction has been completed
14.1 Verilog Statements Introduction 14.1 Verilog Statements Introduction has been completed
14.2 Always Statements 14.2 Always Statements has been completed
14.3 Multiple Assignments in Always Statements 14.3 Multiple Assignments in Always Statements has been completed
14.4 Blocking and Non-blocking 14.4 Blocking and Non-blocking has been completed
14.5 When to use Blocking and Non-blocking 14.5 When to use Blocking and Non-blocking has been completed
14.0 Solutions
14.0 Piazza Discussion ThreadThis is an external link.

15.0 Counters

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15.0 Introduction
15.1 T Flip-Flop 15.1 T Flip-Flop has been completed
15.2 Enable 15.2 Enable has been completed
15.3 Examples in Verilog 15.3 Examples in Verilog has been completed
15.4 Synchronous and Asynchronous 15.4 Synchronous and Asynchronous has been completed
15.0 Solutions
15.0 Piazza Discussion ThreadThis is an external link.

16.0 Timing Analysis

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module items
16.0 Introduction
16.1 Basic Timing 16.1 Basic Timing has been completed
16.2 Timing Analysis - Fmax 16.2 Timing Analysis - Fmax has been completed
16.3 Timing Analysis - Hold Check 16.3 Timing Analysis - Hold Check has been completed
16.4 Clock Skew 16.4 Clock Skew has been completed
16.0 Solutions
16.0 Piazza Discussion ThreadThis is an external link.

17.0 Finite State Machines

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17.0 Introduction
17.1 Define FSM 17.1 Define FSM has been completed
17.2 FSM Design 17.2 FSM Design has been completed
17.3 Verilog FSM 17.3 Verilog FSM has been completed
17.4 Mealy Design 17.4 Mealy Design has been completed
17.5 Mealy Verilog 17.5 Mealy Verilog has been completed
17.6 One Hot Encoding 17.6 One Hot Encoding has been completed
17.7 FSM Control of a Data Path 17.7 FSM Control of a Data Path has been completed
17.8 FSM Minimization 17.8 FSM Minimization has been completed
17.0 Solutions
17.0 Piazza Discussion ThreadThis is an external link.

18.0 Memory

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module items
18.0 Introduction
18.1 Memories 18.1 Memories has been completed
18.2 Address Decoder 18.2 Address Decoder has been completed
18.3 Tri State Buffer 18.3 Tri State Buffer has been completed
18.4 Memory Cell Matrix - The Memory Cell 18.4 Memory Cell Matrix - The Memory Cell has been completed
18.5 Memory Cell Matrix 18.5 Memory Cell Matrix has been completed
18.6 Synchronous Memory Timing 18.6 Synchronous Memory Timing has been completed
18.7 Memory inside the FPGA - synchronous timing 18.7 Memory inside the FPGA - synchronous timing has been completed
18.8 SDRAM - what's on DE1-SoC 18.8 SDRAM - what's on DE1-SoC has been completed
18.0 Solutions
18.0 Piazza Discussion ThreadThis is an external link.

19.0 Signed Numbers

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module items
19.0 Introduction
19.1 Representations 19.1 Representations has been completed
19.2 Addition & Subtraction 19.2 Addition & Subtraction has been completed
19.3 Conversion Sign Extension 19.3 Conversion Sign Extension has been completed
19.4 Verilog Notation 19.4 Verilog Notation has been completed
19.0 Solutions
19.0 Piazza Discussion ThreadThis is an external link.

20.0 Fast Adders

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20.0 Introduction
20.1 Carry Lookahead 20.1 Carry Lookahead has been completed
20.2 Hybrid Architecture 20.2 Hybrid Architecture has been completed
20.3 Hierarchical P and G 20.3 Hierarchical P and G has been completed
20.0 Solutions
20.0 Piazza Discussion ThreadThis is an external link.

21.0 More Arithmetic

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module items
21.0 Introduction
21.1 Multiplier 21.1 Multiplier has been completed
21.2 Arithmetic Overflow 21.2 Arithmetic Overflow has been completed
21.3 Arithmetic Coding in Verilog 21.3 Arithmetic Coding in Verilog has been completed
21.0 Solutions
21.0 Piazza Discussion ThreadThis is an external link.

22.0 More Verilog

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module items
22.0 Introduction
22.1 More Bit Width Rules 22.1 More Bit Width Rules has been completed
22.2 Verilog Parameters 22.2 Verilog Parameters has been completed
22.3 Wires vs Reg 22.3 Wires vs Reg has been completed
22.0 Solutions
22.0 Piazza Discussion ThreadThis is an external link.

23.0 Multiplexer Logic

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module items
23.0 Introduction
23.1 Examples 23.1 Examples has been completed
23.2 Shannon's Expansion System 23.2 Shannon's Expansion System has been completed
23.3 Shannon with multiple variables 23.3 Shannon with multiple variables has been completed
23.4 LUT synthesis 23.4 LUT synthesis has been completed
23.0 Solutions
23.0 Piazza Discussion ThreadThis is an external link.

24.0 More Combinational Blocks

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24.0 Introduction
24.1 Decoders 24.1 Decoders has been completed
24.2 Priority Encoder 24.2 Priority Encoder has been completed
24.3 Arithmetic Comparator 24.3 Arithmetic Comparator has been completed
24.0 Piazza Discussion ThreadThis is an external link.

25.0 Simple Processor

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module items
25.0 Introduction
25.1 Processor Definition 25.1 Processor Definition has been completed
25.2 Instructions 25.2 Instructions has been completed
25.3 Execution of Instructions 25.3 Execution of Instructions has been completed
25.4 Verilog Sketch 25.4 Verilog Sketch has been completed
25.5 Enhanced Verilog 25.5 Enhanced Verilog has been completed
25.0 Solutions
25.0 Piazza Discussion ThreadThis is an external link.

26.0 Transistors

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module items
26.0 Introduction
26.1 As switches MOSFETs 26.1 As switches MOSFETs has been completed
26.2 Inverter 26.2 Inverter has been completed
26.3 CMOS NAND-NOR 26.3 CMOS NAND-NOR has been completed
26.4 Complex CMOS Gates 26.4 Complex CMOS Gates has been completed
26.5 AND Gate-Body Effect 26.5 AND Gate-Body Effect has been completed
26.6 Transmission Gates 26.6 Transmission Gates has been completed
26.7 Fan In 26.7 Fan In has been completed
26.0 Solutions
26.0 Piazza Discussion ThreadThis is an external link.

27.0 Synchronizers

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27.1 Synchronizers
27.1 Synchronizers Video 27.1 Synchronizers Video has been completed
27.0 Solutions
27.0 Piazza Discussion ThreadThis is an external link.

Suggested Practice Questions (from the Textbook)

module items
Suggested_Practice_Problems.pdf
Practice problem solutions

Prof. Korst's Notes (after Midterm)

module items
ECE241 post midterm materialThis is an external link.